So far, the MOS transistor has been integrated more highly by downsizing, whereby high speed and low electric power consumption have been attained. However, the downsizing of the MOS transistor depending on the scaling rule is coming to the limit. Studies of technologies of enhancing the performance of the MOS transistor by means which does not depend on the downsizing are becoming active.
For example, studies of the technology of introducing a strain in the channel region of the MOS transistor to thereby change properties of the channel material so as to improve the carrier mobility are becoming active.
As one example of the technology of introducing the strain in the channel region is known the technology that stresses is applied to the channel region by the etching stopper film for forming the contact holes to thereby introduce the strain in the channel region. As such etching stopper film, a tensile stressor film having a tensile stress is formed over the NMOS transistor. Over the PMOS transistor, a compressive stressor film having a compressive stress is formed.
FIG. 24 is a diagrammatic section view of the conventional semiconductor device of the CMOS structure having strains introduced in the channel regions by the tensile stressor film and the compressive stressor film.
As illustrated, a device isolation film 102 for defining device regions is formed in a surface of a silicon substrate 100. The device region on the left side of the drawing is an NMOS transistor forming region, and the device region on the right side of the drawing is a PMOS transistor forming region.
Over the silicon substrate 100 in the NMOS transistor forming region, a gate electrode 106n is formed with a gate insulating film 104 interposed therebetween. On a side wall of the gate electrode 106n, a sidewall insulating film 108 is formed.
In the silicon substrate 100 on both sides of the gate electrode 106n, n-type source/drain regions 110n having the extension source/drain structure are formed.
On the gate electrode 106n and the n-type source/drain regions 110n, metal silicide films 112 are formed.
Thus, on the silicon substrate 100 in the NMOS transistor forming region, an NMOS transistor 114n including the gate electrode 106n and the n-type source/drain regions 110n is formed.
Over the NMOS transistor 114n, a tensile stressor film 116 having a tensile stress is formed, covering the NMOS transistor 114n. As the tensile stressor film 116, a silicon nitride film having a tensile stress is formed. In the channel region of the NMOS transistor 114n, a strain due to the stress applied by the tensile stressor film 116 is introduced.
Over the silicon substrate 100 in the PMOS transistor forming region, a gate electrode 106p is formed with a gate insulating film 104 interposed therebetween. On a side wall of the gate electrode 106p, a sidewall insulating film 108 is formed.
In the silicon substrate 100 on both sides of the gate electrode 106p, p-type source/drain regions 110p having the extension source/drain structure are formed.
On the gate electrode 106p and the p-type source/drain regions 110p, metal silicide films 112 are formed.
Thus, on the silicon substrate 100 in the PMOS transistor forming region, a PMOS transistor 114p including the gate electrode 106p and the p-type source/drain regions 110p is formed.
Over the PMOS transistor 114P, a compressive stressor film having a compressive stress is formed, covering the PMOS transistor 114p. As the compressive stressor film 118, a silicon nitride film having a compressive stress is formed. In the channel region of the PMOS transistor 114p, a strain due to the stress applied by the compressive stressor film 118 is introduced.
As described above, the CMOS structure of the combination of the NMOS transistor 114 having the strain introduced in the channel region by the tensile stressor film 116, and the PMOS transistor 114p having the strain introduced in the channel region by the tensile stressor film 118 can increase the strains introduced in the channel regions and improve the carrier mobility at low costs by optimizing the respective sectional structures of the NMOS transistor 114n and the PMOS transistor 114p. 
The followings are examples of related art of the present invention: S. E. Thompson et al., “A 90-nm logic technology featuring strained-silicon,” IEEE Trans. Elec. Dev., Vol. 51, No. 11, pp. 1790-1797, November 2004; C.-H. Ge et al., “Process-strained-Si (PSS) CMOS technology featuring 3D strain engineering,” IEDM Tech. Dig., 2003, pp 73-76; and C. S. Smith, “Piezoresistance effect in germanium and silicon,” Phys. Rev., vol. 94, No. 1, pp. 42-49, 1954.
However, in the semiconductor device of the CMOS structure illustrated in FIG. 24, when the NMOS transistor and the PMOS transistor include the sidewall insulating films of the same structure, it is difficult to improve the characteristics of both.